1. Technical Field
The present invention relates to a switching driver, in particular, to a switching driver capable of reducing EMI effect and power ripple.
2. Description of Related Art
Because of the advantages of high efficiency, the switching driver is widely applied in class-D power amplifiers with high wattage, to provide high current to a load. The class-D power amplifier adopts the switching driver to modulate signals. However, it is easy to cause the problem of generating power ripple and EMI effect in the output end of the switching driver.
Please refer to FIG. 1, which shows a diagram of a traditional switching driver. As shown in FIG. 1, the switching driver 10 is used in a class-D power amplifier, which includes a non-overlapping signal generator 12, a high-side driver 14, a low-side driver 16, a high-side switch MH, and a low-side switch ML. The non-overlapping signal generator 12 generates a first non-overlapping signal S1 and a second non-overlapping signal S2 according to a pulse width control signal Sp, to avoid turning on the high-side switch MH and the low-side switch ML at the same time. In general, the pulse width control signal Sp is generated by the pulse-width modulator, to adjust the duty cycle of the first non-overlapping signal S1 and the second non-overlapping signal S2.
The high-side driver 14 generates a first switching signal Sup according to the first non-overlapping signal S1, to control the turning on and turning off of the high-side switch MH. The low-side driver 16 generates a second switching signal Sdn according to the second non-overlapping signal S2, to control the turning on and turning off of the low-side switch ML. An output end OUT is configured between the high-side switch MH and the low-side switch ML. The output end OUT outputs an output signal So to a load 19 according to a power voltage VDD.
In general, this may cause the leakage current of low impedance from the power end to the ground end because of turning on the high-side switch MH and the low-side switch ML at the same time. In order to avoid the leakage current, the non-overlapping signal generator 12 simultaneously turns off the high-side switch MH and the low-side switch ML for a period of time (called dead-time) before turning on the high-side switch MH or the low-side switch ML, to cause the output end OUT to be operating in a high impedance state. If the load 19 is an inductive load (e.g., a speaker), the output end OUT suffers from the influence of the load current, to increase the output signal So (see FIG. 1) (i.e., the load current flowing in the output end OUT) or decrease the output signal So (i.e., the load current flowing out the output end OUT) during the dead-time. The load current becomes higher, and the slope of the output signal So of the output end OUT becomes higher, thereby causing EMI effect.
Even if the high-side switch MH and the low-side switch ML are turned off during the dead-time, the parasitic diodes of the high-side switch MH and the low-side switch ML are turned on by the load current, so that the voltage of the output end OUT is higher than the voltage of the power end or lower than the voltage of the ground end, to cause power ripple.
For example, please refer to FIG. 2 in conjunction with FIG. 1. When the pulse width control signal Sp is converted from the low level to the high level, the switching driver 10 may enter a period of dead-time DT1. During the dead-time DT1, the first non-overlapping signal S1 stays low level, and the second non-overlapping signal S2 is converted from the high level to the low level. At this time, the gate voltage Vgsu of the high-side switch MH is lower than the turn-on voltage, to keep the high-side switch MH in off state. The gate voltage Vgsd of the low-side switch ML decreases from a high voltage to less than the turn-on voltage, to turn off the low-side switch ML. So that the high-side switch MH and the low-side switch ML are off during the dead-time DT1. In this period, when the load current flows into the output end OUT, the output signal So of the output end OUT increases quickly (e.g., the period SR1 shown in FIG. 2) until the parasitic diode of the high-side switch MH turned on. The load current finally flows into the power voltage VDD and disturbs it. The output end OUT with fast slew rate and high frequency oscillation generates EMI in period DT1 shown in FIG. 2 until the high-side switch MH is turned on completely.
Similarly, when the pulse width control signal Sp is converted from the high level to the low level, the switching driver 10 may enter a period of dead-time DT2. During the dead-time DT2, the high-side switch MH and the low-side switch ML are turned off. In this period, when the load current flows out the output end OUT, the output signal So of the output end OUT decreases quickly (e.g., the period SR2 shown in FIG. 2) until the parasitic diode of the low-side switch ML turned on. The load current finally flows from ground and disturbs it. The output end OUT with fast slew rate and high frequency oscillation generates EMI in period DT2 shown in FIG. 2 until the low-side switch ML is turned on completely.
Therefore, how to reduce EMI effect and power ripple generated from the switching driver 10 operating in the dead-time has become a major issue.